On Wed, 24 Jul 2002 14:02:52 EDT, David Wheeler <dwheelerat_private> said: > But this patch DOES NOT FULLY SOLVE THE PROBLEM OF POINTER WRITES BEING > NON-ATOMIC on the obnoxious CPU architectures if there's > 1 CPU. I know of no currently used CPU designs that have an actual non-atomic write of a pointer unless the pointer is misaligned (the S/370-XA architecture allows piecemeal storing, but I don't think any models actually did it on an aligned fullword store). Presumably, gcc made the pointers aligned, so unless I'm missing something REALLY subtle this should be a mostly non-issue. Personally, I'd worry more about cache coherency issues - there are 4 important points in a 'store to memory' operation: 1) When CPU 1 sends the word to L1/L2 cache 2) When CPU 1's cache controller flushes the cache line to main memory. 3) When CPU 2 notices the line it already has in L1/L2 cache is invalid 4) When CPU 2 actually loads a valid cache line from main memory (Yes, I know 3 and 4 are "logically" the same time from CPU 2's point of view - but Murphy guarantees that if CPUs 1 and 2 are running code that's in a race, CPU 3 will be in that code TOO (think multiple CPU's all waiting on the same spinlock), and will be doing its best to create another race between (3) and (4)). At least on the S/390 from IBM, the architecture specifically states that other CPUs may not actually see a store to memory happen for an *indefinite* amount of time - until a serialization event happens (if you've ever had to code 'bcr 15,0' on an IBM, you know what I mean). -- Valdis Kletnieks Computer Systems Senior Engineer Virginia Tech
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