Valdis.Kletnieksat_private wrote: > Assuming a really smart hardware implementation, you can probably get it > down to around 32 cycles (assuming a PAL to do the S-box and other stuff), > doing each of 16 rounds in 2 cycles. In hardware you can unroll the loop and use pipelining giving even 1 cycle per 1 block of data (not to mark about paralel processing which is easy with today's FPGAs). -- Slawek
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