On Wed, 09 Apr 2003 20:45:47 +0200, Slawek said: > In hardware you can unroll the loop and use pipelining giving even 1 cycle > per 1 block of data (not to mark about paralel processing which is easy with > today's FPGAs). Well.. one externally visible cycle - if you unroll the loop you need to either have 16 cascading stages that use async logic or timing signals to keep all the bits in sync. ;) I wonder how many clock cycles it would take using a 2901 bitslice (anybody remember those? ;)
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