Valdis.Kletnieksat_private wrote: >> In hardware you can unroll the loop and use pipelining giving even 1 cycle >> per 1 block of data (not to mark about paralel processing which is easy with >> today's FPGAs). > > Well.. one externally visible cycle - if you unroll the loop you need to either > have 16 cascading stages that use async logic or timing signals to keep all the > bits in sync. ;) You have n hardware gates making simple operations each with proper latches as needed, all latches use the same clock signal. One data is encoded in L cycles, but a new data set is started in every one cycle. So yes - processing of one dataset takes L cycles, but processing for example 1G datasets takes 1G +L-1 cycles. -- Slawek
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