Valdis.Kletnieksat_private wrote: > > In hardware you can unroll the loop and use pipelining giving even > > 1 cycle per 1 block of data (not to mark about paralel processing > > which is easy with today's FPGAs). > > Well.. one externally visible cycle - if you unroll the loop you > need to either have 16 cascading stages that use async logic or > timing signals to keep all the bits in sync. ;) Theoretically you could just expand the operation to minterms (sum-of-products), although it might result in a rather large chip. If you have enough gates, any computation on fixed-sized inputs can be performed solely by combinatorial logic (i.e. "in one cycle"). -- Glynn Clements <glynn.clementsat_private>
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